1. Field of the Invention
The present invention generally relates to semiconductor memory devices and memory erasure methods, and particularly relates to a nonvolatile semiconductor memory device and a method of erasing nonvolatile memory cells.
2. Description of the Related Art
Flash memories are widely used as nonvolatile semiconductor memory devices that allow memory cells to be electrically written and erased. An erase operation in flash memories is performed as a block erase for the entire memory cell array or a block erase on a block-by-block basis. Namely, memory cells are erased together in a lump with respect to the entire memory cell array or with respect to a specific one of the blocks into which the memory cell array is divided.
In the flash memories, electrons are injected into or removed from the floating gate of a memory cell, thereby performing a write operation and an erase operation with respect to the memory cell. As one of the characteristics of the flash memories, the threshold voltage of a memory cell is determined in response to the amount of electrons trapped in the floating gate. By utilizing this, the high-threshold voltage state (written state) in which electrons are trapped in the floating gate is assigned to logic “0”, and the low-threshold voltage state (erased state) in which electros have been removed from the floating gate is assigned to logic “1”.
In the flash memories, erase speed differs from memory cell to memory cell due to manufacturing variation in the thickness and/or minute defect of the oxide film of the transistor constituting a memory cell. Even when identical erase operations are performed, therefore, a cell that is easy to erase is set to a low threshold voltage, and a cell that is difficult to erase is set to a high threshold voltage. As a result, the threshold voltages of memory cells are not set constant, and end up having a certain distribution that may be defined with respect to the memory cells of a memory cell array.
FIG. 1 through FIG. 3 are drawings for explaining a memory erase operation in a conventional flash memory. In each of the drawings, the horizontal axis represents the threshold voltage of memory cells of a memory cell array, and the vertical axis represents the number of memory cells present in the memory cell array that have a given threshold voltage.
In order to erase the entire memory cell array or the block to be erased (hereinafter referred to as a memory cell array for the sake of convenience), a “preliminary write” operation is performed that places each memory cell of the memory cell array in the written state. To this end, a write verify that compares the current running through a reference cell having threshold voltage VTp as shown in FIG. 1 with the read current of each cell of the memory cell array is performed. A write operation with respect to each memory cell is performed until each memory cell of the memory cell array is placed in the written state by passing the write verify. After the “preliminary write”, as shown as a distribution D2 in FIG. 2, the threshold voltages of all the memory cells are set higher than VTp, which corresponds to the logic “0” state.
Thereafter, a block erase is performed with respect to the memory cell array after the “preliminary write”. To this end, an erase verify that compares the current running through a reference cell having threshold voltage VTe as shown in FIG. 2 with the read current of each cell of the memory cell array is performed. A block erase operation with respect to the memory cell array is performed until each memory cell of the memory cell array is placed in the erased state by passing the erase verify. As a result, as shown as a distribution D3 in FIG. 3, the threshold voltages of all the memory cells are set lower than VTe, which corresponds to the logic “1” state.
The reason why the preliminary write operation is performed prior to an erase operation will be described in the following. In a memory cell array prior to erasure, memory cells having logic “1” conforming to a distribution D11 and memory cells having logic “0” conforming to a distribution D10 are in existence as shown in FIG. 1. When the memory cells are subjected to a block erase, all the memory cells are erased in the same manner. As a result, the memory cells having logic “1” at the beginning tend to end up having a lower threshold than the memory cells having logic “0” at the beginning. Because of this, the distribution of threshold voltages of all the memory cells ends up being an extremely wide distribution. In order to avoid such an extremely wide threshold voltage distribution, a preliminary write operation is performed prior to an erase operation as described above.
In flash memories, voltage VWLs is applied to the selected word line, and voltage VWLu is applied to the unselected word lines in order to read data from memory cells. Further, voltage VLWs is applied to the word line of the read reference cell. This read reference cell has threshold voltage VTr. The voltage VLWs, voltage VWLu, and threshold voltage VTr are shown in FIG. 1 through FIG. 3.
The current of a memory cell coupled to the selected word line is compared with the current of the reference cell by a sense amplifier. If the current of the memory cell is larger (i.e., if the threshold voltage is lower), logic “1” is detected. If the current of the memory cell is smaller (i.e., if the threshold voltage is higher), logic “0” is detected.
The upper limit of the threshold voltage of a memory cell having logic “1” is controlled by the erase verify reference voltage VTe (i.e., the threshold voltage of the erase-verify-purpose reference cell). In order to properly detect a memory cell having logic “1” as being logic “1”, the read reference cell threshold voltage VTr needs to be higher than the erase verify reference voltage VTe by a predetermined voltage ΔVT1. The value of the predetermined voltage ΔVT1 depends on the characteristics of the sense amplifier and required read speed.
Since there is a need to flow a current through the reference cell to be compared at the time of read operation, the selected-word-line voltage VWLs needs to be higher than the read reference cell threshold voltage VTr by a predetermined voltage ΔVT0. The value of the predetermined voltage ΔVT0 depends on the required read speed.
Accordingly, in order to correctly read the values of memory cells having the threshold voltage distributions as shown in FIG. 1, the selected-word-line voltage VWLs needs to be set higher than the erase verify reference voltage VTe by ΔVT1+ΔVT0. IF VTe=2.5 V, ΔVT1=0.5 V, and ΔVT0=1 V, for example, the selected-word-line voltage VWLs is 4 V. In this case, a 5-V power supply voltage applied to the flash memory can easily generate a proper word line voltage.
In recent years, however, the power supply voltage of flash memories has generally been lowered from 5 V to 3 V and further to 1.8 V. In order to generate a proper selected-word-line voltage VWLs from a low power supply voltage, there is a need to step-up the voltage. Such stepping-up of voltage, however, results in an increase in electric current consumption, which gives rise to a need to suppress the selected-word-line voltage VWLs as low as possible.
In order to lower the selected-word-line voltage VWLs in FIG. 1 through FIG. 3, it suffices to lower the erase verify reference voltage VTe. If the erase verify reference voltage VTe is lowered, however, the threshold voltage distribution D3 after the erase operation ends up being shifted, as a whole, to a lower voltage. In this case, memory cells situated close to the left end of the threshold voltage distribution D3 are undesirably placed in the over-erased state. When a memory celli is in the over-erased state, a current constantly runs through the memory cell even if the unselected-word-line voltage VWLu is applied to the word line. As a result, the current of such unselected memory cell is added to the current of a selected memory cell, making it difficult to perform a proper read operation.
[Patent Document 1] Japanese Patent Application Publication No. 2001-184876
[Patent Document 2] Japanese Patent Application Publication No. 2003-162896
Accordingly, there is a need for a nonvolatile semiconductor memory device and a memory cell erase method that can achieve a threshold voltage distribution after the erase operation that is narrower than conventional distributions.